Exposing pipeline interlocks, enabling compiler optimizations to reduce blockage between stages.Īdditionally, some ARM9 cores incorporate 'Enhanced DSP' instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.

This is helped by both the modified Harvard architecture (reducing bus and cache contention) and the new pipeline stages. Faster loads and stores many instructions now cost just one cycle.Many unmodified ARM7 binaries were measured as taking about 30% fewer cycles to execute on ARM9 cores. Shifting from a three-stage pipeline to a five-stage one lets the clock speed be approximately doubled, on the same silicon fabrication process. Decreased heat production and lower overheating risk.Key improvements over ARM7 cores, enabled by spending more transistors, include: There are two subfamilies, implementing different ARM architecture versions. Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories. With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a (modified meaning split cache) Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed. See also: ARM architecture and List of ARM cores

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